1. Field of the Invention
The present invention generally relates to a follower, in particular, to a source follower.
2. Description of Related Art
Since liquid crystal should be driven by voltage, in a liquid crystal driving chip adopted by a liquid crystal display (LCD), voltage follower circuits of different architectures may be employed as output buffers. FIG. 1 shows an architecture of a conventional voltage follower circuit. Referring to FIG. 1, the voltage follower circuit is constituted by source followers 110 and 120. The source follower 110 includes switches 111, 113, 115 and NMOS transistors 112, 114. The source follower 120 includes switches 121, 123, 125 and PMOS transistors 122, 124. Further, in FIG. 1, VCC is the supply voltage, GND is the ground voltage, DATA is the input signal, OUT is the output signal, and SW1, SW2 are switch control signals for controlling the turn on/off of the switches.
The disadvantage of using the conventional source follower to realize the voltage follower circuit in FIG. 1 is that, the output voltage of the voltage follower circuit is limited by a threshold turn-on voltage (Vth) of the MOS transistor, and thus a rail-to-rail operation cannot be achieved. Referring to FIG. 1, the voltage level of the output signal OUT cannot reach the levels of the supply voltage VCC and the ground voltage GND. The reason of the above problem is explained with reference to FIG. 2.
FIG. 2 is a signal timing chart of the circuit in FIG. 1. Referring to FIGS. 1 and 2 together, during a pre-charging period of T2, the switch control signal SW1 is at a low level, and the switch control signal SW2 is at a high level for some time durations. During the period that the switch control signal SW2 is at a high level, the switches 111, 115, 121, 125 are turned off, and the switches 113, 123 are turned on, so a gate voltage VNGATE of the NMOS transistor 114 is charged to the level of the supply voltage VCC, and a gate voltage VPGATE of the PMOS transistor 124 is at the level of the ground voltage GND. During a data transmission period of T1, the switch control signal SW1 is at a high level, and the switch control signal SW2 is at a low level, so the switches 111, 115, 121, 125 are turned on, and the switches 113, 123 are turned off. At this time, as the gate voltage VNGATE=DATA+VGSN, the voltage level of the output signal OUT may be expressed by Formula (1) as follows:VOUT=(VNGATE−VGSN)=(DATA+VGSN−VGSN)  Formula (1)where VOUT is a voltage level of the output signal OUT, and VGSN is a gate-source voltage of the NMOS transistors.
Seen from the Formula (1), VOUT=DATA. However, when the highest voltage of the input signal DATA is equal to the level of the supply voltage VCC, as the gate voltage VNGATE can only be raised to the level of the supply voltage VCC at most, the highest voltage of the output signal OUT may be expressed by Formula (2) as follows:VOUT=(VNGATE−VGSN)=(VCC−VGSN)  Formula (2).
Thus, seen from Formula (2), when the level of the input signal DATA is equal to that of the supply voltage VCC, the highest voltage of the output signal OUT cannot reach the level of the supply voltage VCC. Similarly, when the lowest voltage of the input signal DATA is equal to the level of the ground voltage GND, as VOUT=(GND+VSGP), in which VSGP is a source-gate voltage of the PMOS transistors, the lowest voltage of the output signal OUT cannot reach the level of the ground voltage GND. Therefore, if the architectures of the source followers shown in FIG. 1 are employed to achieve a voltage follower circuit, the voltage swing of the output signal OUT may not reach the levels of the supply voltage VCC and the ground voltage GND, such that the voltage follower circuit cannot achieve the rail-to-rail operation.